Browse Prior Art Database

Computer Accessible Digital Clock

IP.com Disclosure Number: IPCOM000078511D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Clarke, EP: AUTHOR [+3]

Abstract

There is described an arrangement for providing an accurate, synchronized time standard for a computer center, i.e., one which contains a plurality of computing systems. With this arrangement, time information is program accessible to all of the computing systems and is available for displays.

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Computer Accessible Digital Clock

There is described an arrangement for providing an accurate, synchronized time standard for a computer center, i.e., one which contains a plurality of computing systems. With this arrangement, time information is program accessible to all of the computing systems and is available for displays.

The arrangement is shown in Fig. 1. As seen, it comprises a basic clock 10, which is a crystal-controlled oscillator suitably of a 100KHz frequency, the clock including appropriate countdown circuits to format the time information in a conventional way. Associated with clock 10 is a local display 12 which is suitably housed in the same unit as the basic clock and reads out on the numeric display tubes, as shown in Fig. 2. Subdivisions of a small fraction of a second such as
0.0001 second can be made accessible to program readings, but these fractions need not be displayed. Clock 10 and display 12 are provided with a power supply 14 which can suitably be a converter, for converting available commercial AC power to DC as required. The battery take-over circuit 16 is included to assure that the clock continues to run and thereby remain accurate, independent of AC power loss or power dips. The stages designated by numeral 18 are standard I/O interfaces which appear as control units to any channel on a control system. They are controlled by standard programming techniques to enable the computing system to read the clock information.

As shown in Fig. 1, there are provided 1 to N standard I/O interfaces, each of these interfaces being associated through an appropriate channel with an equal number, i.e., 1 to N computing systems, generally designated by the numeral 20. Remote displays designated by the numeral 22 and similar to local display 12 can be inserted into the arrangement for use where required.

The hub of the arrangement is the stage 24, legended distributor. This stage intercommunicates with clock 10, I/O interfaces 18 and remote displays 22, and consists of logic and power circuitry to drive the timing information to the interfaces...