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Direct Form Digital Filter Using Floating Point Arithmetic

IP.com Disclosure Number: IPCOM000078513D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Esteban, D: AUTHOR

Abstract

Shown is a digital filter in which coefficients are coded in 2's complement normalized floating point. A number N in 2's complement binary code can be represented using a floating-point base 2 power. N = m.2/c/ where m is the mantissa, m < 1 and c the characteristic.

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Direct Form Digital Filter Using Floating Point Arithmetic

Shown is a digital filter in which coefficients are coded in 2's complement normalized floating point. A number N in 2's complement binary code can be represented using a floating-point base 2 power. N = m.2/c/ where m is the mantissa, m < 1 and c the characteristic.

Fig. 1 shows a digital filter of the type performing the equation:

(Image Omitted)

when Yn is the nth output sample, alpha i the K coefficients of the filter, and Xn,i the K input samples used for computing the output sample Yn.

The input samples, coded in 16-bit words in the example shown, are applied from shift register SR1 to a fixed-point binary multiplier M through switch SW, which illustrates a time multiplexer.

Multiplier M performs the multiplication of input word Xn,i by the corresponding coefficient alpha i mantissa. In order to avoid taking into account the sign of the results of the multiplications of their accumulation, the 16-bit result words from multiplier M are expanded into 32-bit words, their sign bits being repeated sixteen times. In order to provide expanded results without loss in processing speed, two 16-bit words, results of two consecutive multiplications, are expanded into 32-bit words on a flip-flop basis and added in binary adder sigma before being accumulated in a 32-bit accumulator ACC.

The device which performs 16 to 32 bit expansion comprises inverters I, AND gates 1-4, 0R gates 5-6, delay elements 7-8 each of which introduces a T delay equal to the time interval between two bits, and shift register SR2 which introduces a 16T delay. The operation of the expansion will be described by referencing to Fig. 2, which shows the clock signal CK and the bit sequences at nodes X-Y and Z of the filter of Fig. 1.

Assuming that the clock CK is down, the first 16-bit result word A1, A2 .. As, provided by multiplier M is fed into shift register SR2 t...