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Fast Power Line Failure Detector

IP.com Disclosure Number: IPCOM000078516D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Hellwarth, GA: AUTHOR [+2]

Abstract

A power failure warning signal following a primary power line droop or outage is provided within 1/2 cycle of a power line failure, by rectifying and summing separate but phase related signals from each power line phase. The circuit permits adjustment for setting the detector level and can include relay contacts to provide an autorestart signal, to power sequencing circuits to automatically power on the machine following a power outage. The circuit is particularly useful for systems having volatile memory and limited power supply energy storage.

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Fast Power Line Failure Detector

A power failure warning signal following a primary power line droop or outage is provided within 1/2 cycle of a power line failure, by rectifying and summing separate but phase related signals from each power line phase. The circuit permits adjustment for setting the detector level and can include relay contacts to provide an autorestart signal, to power sequencing circuits to automatically power on the machine following a power outage. The circuit is particularly useful for systems having volatile memory and limited power supply energy storage.

The power failure detector consists of a phase lead-lag network 11, to provide two phases 15 and 16 of power line voltage 10 in quadrature for each single input phase, followed by two full-wave detectors 18, a summing point 20, a low-pass filter 21, a comparator amplifier 22, and an input reference voltage with positive feedback for hysteresis.

The phase lead-lag circuit 11 preferably uses an input from the center tapped secondary of an isolation transformer. Each input is fed in parallel through a phase lead and a phase-lag circuit, each consisting of a resistor and capacitor matched to give a 45 degree lead or lag. The four resulting outputs are then detected by diodes and fed to the filter 21 and comparator amplifier 22. Phase lead-lag circuit 11 essentially doubles the detector output ripple frequency, as shown by the waveform. The diode detector 18 and filter 21 react to loss of input within 1/2 cycle of the input frequency, which is within 8 milliseconds for 50-60 hertz power. That is, the filter 21 time constant is chosen so that the circuit reacts to a power loss within 1/2 cycle, but minimizes the ripple on the detector 18 output.

Comparator amplifier 22 can be a high-gain,...