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Complimentary Bi FET Logic Circuitry

IP.com Disclosure Number: IPCOM000078541D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Blose, WL: AUTHOR [+2]

Abstract

Described is a semiconductor configuration that can function as a complementary metal-oxide silicon (MOS) circuit or a complementary Bipolar Circuit while utilizing essentially the same devices and I/O connections. The basic circuit can function as a SET/RESET FLIP-FLOP (S/R F/F), by a simple feedback path providing a "DOUBLE SET -SINGLE RESET" latch. Logically, the circuit of Fig. 1 functions as an AND-NAND block.

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Complimentary Bi FET Logic Circuitry

Described is a semiconductor configuration that can function as a complementary metal-oxide silicon (MOS) circuit or a complementary Bipolar Circuit while utilizing essentially the same devices and I/O connections. The basic circuit can function as a SET/RESET FLIP-FLOP (S/R F/F), by a simple feedback path providing a "DOUBLE SET -SINGLE RESET" latch. Logically, the circuit of Fig. 1 functions as an AND-NAND block.

Operation of the circuit is as follows: With both inputs A and B at an UP- LEVEL or Logical 1, device 1 is biased OFF. This keeps device 2 off and the output at Node X represents the AND of the inputs. Devices 3 and 4 are active load devices. If either input A or B or both are at a DOWN-LEVEL or Logical 0, device 1 is forward biased and conducts base current from device 2, turning it ON. This causes Node X to move to a DOWN LEVEL or Logical 0. If load device 4 is moved to the collector lead of device 2, the circuit performs a NAND function.

Fan-in can be increased by adding emitters to device 1 and/or dotting more NPN devices at Node Z. An advantage of this circuit over the conventional T/2/L circuit is that with increasing fan-in device 2 is not driven further toward saturation, since the base drive remains essentially constant.

A diffusion profile of the circuit is shown in Fig. 2.

The corresponding schematic is shown in Fig. 3.

The complementary field-effect transistor (FET) circuit configuration is shown in Fig....