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Array ALU with Full Word Binary, Logical, and Decimal

IP.com Disclosure Number: IPCOM000078542D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR [+3]

Abstract

Semiconductor arrays and a minimum of logical circuits provide a high-speed ALU, with full-word binary and decimal add and full-word logical operations. The usual decimal correction circuits are eliminated. Each four-bit stage of a word (32 bits) is provided two arrays, each producing a four-bit answer, parity bit and carry bit. The output of one array is gated if there is a carry in; the output of the other array, if there is no carry in. Carry logic for the eight four-bit stages produces only five stage delays, whereby full-word decimal add (the slowest operation) requires only the delay of the array and the five stage delays. In existing technology, the total delay can be significantly less than one hundred nanoseconds.

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Array ALU with Full Word Binary, Logical, and Decimal

Semiconductor arrays and a minimum of logical circuits provide a high- speed ALU, with full-word binary and decimal add and full-word logical operations. The usual decimal correction circuits are eliminated. Each four-bit stage of a word (32 bits) is provided two arrays, each producing a four-bit answer, parity bit and carry bit. The output of one array is gated if there is a carry in; the output of the other array, if there is no carry in. Carry logic for the eight four-bit stages produces only five stage delays, whereby full-word decimal add (the slowest operation) requires only the delay of the array and the five stage delays. In existing technology, the total delay can be significantly less than one hundred nanoseconds.

The drawing illustrates the ALU circuits for the low-order byte 3. Arrays 101 and 102, provided for bits 4-7 of byte 3, each include four-bit inputs A and B and three-bit function decode bits which permit eight different functions, e.g. true and complementary binary and decimal add, AND, AND/INVERT, OR and XOR. The arrays 101 and 102 produce, answer, parity and carry outputs A11, P11, C11 and A12, P12, C12, respectively.

The carry-in signal CIN is applied to a driver 3 to gate the 101 or 102 outputs (via true or complement output lines C1S or C1N) through gates 104, 105, 106 to produce the correct answer, a carry signal C2N or C2S (if the operation is arithmetic), and a parity signal.

Arrays 111 and 112 for bits 0-3 of byte 3 produce answer, parity and carry outputs A21, P21, C21 and A22, P22, C22. The proper carry-out signal for byte 3 (bits...