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Differential Automatic Zero Correction Amplifier

IP.com Disclosure Number: IPCOM000078592D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Hellwarth, GA: AUTHOR [+2]

Abstract

A differential amplifier with automatic zero correction provides a very small and relatively constant input offset voltage over periods of time and changing temperatures, by using a DC correction signal that is inserted into an inner stage of the amplifier. A zero-correction interval is employed to measure and hold an amplified version of the input offset with the amplifier's input shorted, so that the stored correction voltage can be used to correct for the amplifier's offset during normal operation.

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Differential Automatic Zero Correction Amplifier

A differential amplifier with automatic zero correction provides a very small and relatively constant input offset voltage over periods of time and changing temperatures, by using a DC correction signal that is inserted into an inner stage of the amplifier. A zero-correction interval is employed to measure and hold an amplified version of the input offset with the amplifier's input shorted, so that the stored correction voltage can be used to correct for the amplifier's offset during normal operation.

The circuit operates with a sequence of two switch controlled intervals, with the switches preferably being low leakage metal-oxide silicon transistors. Fig. 1 shows the general circuit configuration for developing and storing the zero- correction offset potential, while Figs. 2 and 3 illustrate two variations of the dual differential amplifier pairs 10 which can be used in the Fig. 1 configuration. Operation will be first described for Fig. 1 using the Fig. 2 components for 10.

Amplifier operation begins with initiation of the error storage interval by opening switches 11, 12, 17A and 17B, while closing switches 13, 14, 15, 16A and 16B. During this interval, the sum of the equivalent input offset voltages of amplifiers 20 and 21 is amplified and stored by the sample-and-hold circuitry formed by capacitor 25 and amplifier 26. The normal amplification interval is initiated by opening switches 13, 14, 15, 16A and 16B while closing switches 11, 12, 17A and 17B, allowing normal amplification of the input voltages V1 and V2. The correction voltage on capacitor 25 is also applied to the amplifier through the differential outputs 27 and 28 of amplifier 26 and the like...