Browse Prior Art Database

Biasing Technique

IP.com Disclosure Number: IPCOM000078613D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Arnold, RW: AUTHOR [+2]

Abstract

This bias technique is useful for a Darlington differential pair input stage.

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Biasing Technique

This bias technique is useful for a Darlington differential pair input stage.

Transistors 1, 3 and transistors 2, 4 are configured as a Darlington differential pair and are followed by transistors 5, 6, which are configured as a differential pair.

Inputs 7 and 8 are the input terminals of the differential pair 1 to 4. Terminal 9 provides a current signal to the output stage, not shown. A bias current 1 flowing into terminal 10 provides currents J and K (approximately equal to I) to the emitters of differential pairs 5, 6 and transistors 3, 4. It also provides currents M and N (approximately equal to A over B(I)) to the emitters of the input transistors 1 and 2.

Network 10-15 provides current bias for the transistors 1-6. The contribution to input offset error at terminals 7 and 8 due to differences in currents Ie3 and Ie4 not being equal, is not dependent on current K but is set by resistors C. Thus, relatively large errors in the gain from 1 to K do not affect input offset voltage and current. However, errors in M with respect to N directly impact input offset. Because of the utilization of a Darlington differential pair input stage, the emitters of 1 and 2 are a diode drop above those of 3 and 4. This diode drop is available across resistors B for current accuracy without any sacrifice in common mode input range. That is to say, as the voltage at inputs 7 and 8 with respect to minus is reduced, the eventual saturation of transistor 14 cannot b...