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Decoder in Complementary MOS Technology

IP.com Disclosure Number: IPCOM000078618D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Benichou, C: AUTHOR [+2]

Abstract

This decoder uses a prewired matrix made with field-effect transistors (FET's) of the N-channel type. Each N-channel type FET has its source connected to line G (grounded in the case of part A of the figure), its gate connected to one of the outputs of a true complement generator, and its drain connected to a FET of the P-channel type.

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Decoder in Complementary MOS Technology

This decoder uses a prewired matrix made with field-effect transistors (FET's) of the N-channel type. Each N-channel type FET has its source connected to line G (grounded in the case of part A of the figure), its gate connected to one of the outputs of a true complement generator, and its drain connected to a FET of the P-channel type.

In accordance with the logical combination set at the true complement generator input, the selected address line is to be at a high level (supply voltage), the other address lines being at a low level (ground).

For that, all the P-channel type transistors are made to conduct by grounding their gate through line E (This line can be used as a gating control for the decoder). Only one address line will be at a high level when all N-channel FET's associated with this line will be blocked.

In the example shown on part A of the figure, line 10110 will be at a high level if FET's N(4), N(3) ... N(0) are blocked. The N-channel FET's are blocked if their gates are at a low level. Thus, address line 10110 will be at a high level if the true complement generator inputs 2/4/,2/2/,2/1/ are at high level and 2/3/, 2/0/,are at low level. All the other address lines will have at least one of their associated N-channel FET's conducting. For example, address line 10111 will have N(0) transistor conducting.

During the operation of this decoder, a current flows through P and N transistors for the unselected line as long as E is grounded and the true complement generator inputs are present.

The arrangement represented on parts A and B wil...