Browse Prior Art Database

Charge Sensing Circuit

IP.com Disclosure Number: IPCOM000078648D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR

Abstract

The circuit detects small amounts of charge stored in an environment of large capacitive loading, such as is encountered in memory arrays of the type described in U. S. Patent 3,387,286, entitled Field-Effect Transistor Memory.

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Charge Sensing Circuit

The circuit detects small amounts of charge stored in an environment of large capacitive loading, such as is encountered in memory arrays of the type described in U. S. Patent 3,387,286, entitled Field-Effect Transistor Memory.

In the operation of the circuit, clock pulse Phi 3 turns on FET T4 to discharge capacitor C(L), and also capacitor C(BS) through FET T2 since C(G) is charged from a previous cycle. Clock pulse 01 then turns on FET T3 to discharge C(G). Clock pulse 02 is now raised from ground potential to a voltage level V
(1),charging capacitors C (G)and C (L) to approximately V(1) and capacitor C(BS) to approximately V(1) minus the threshold voltage of T2. Clock pulse 03 turns off T4 and the charge on capacitors C(L), C(G) and C(BS) redistributes, until the voltage across capacitor C(BS). plus the threshold voltage of T2 is equal to the voltage across capacitor C(G), at which point T2 turns off. The voltage across C(L) is equal to the voltage across capacitor C(G). Clock pulse Phi1 turns off T3 to trap the charge on capacitor CG.

The voltage level of clock pulse 02 increases to a voltage level V(2), charging capacitor C(L) to V(2) when clock pulse phi 3 again turns on T4. The voltage V(w) on the gate of FET T1 turns on T1, to redistribute charge between capacitor C(N) and capacitor C(BS).

If the voltage across capacitor C(N) was greater than the voltage across capacitor C(BS), the voltage on C(BS) increases, T2 remains off and the...