Browse Prior Art Database

Single Device Cell Using Vertical Junction FET

IP.com Disclosure Number: IPCOM000078651D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR [+2]

Abstract

A small low-power field-effect transistor (FET) type device that can be made with bipolar processes and can use bipolar peripheral circuits is described. As shown in Fig. 1, a P-type substrate 10 has disposed thereon an N+ region 11 and an N-type epitaxial layer 12. A P-type region 13 is diffused into the layer 12 and an N-type region 14 is diffused into the region 13. An isolation region 15 is formed by oxidizing the epi layer 12. This isolation region 15 is made to extend into the substrate 10. The formation of this isolation region 15, causes an N-type skin therein to be created at its interface 16 with epi layer 12. This skin creates an N-type channel 17 past the P-type region 13, so as to interconnect the N-type region 12 and the N-type region 14.

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Single Device Cell Using Vertical Junction FET

A small low-power field-effect transistor (FET) type device that can be made with bipolar processes and can use bipolar peripheral circuits is described. As shown in Fig. 1, a P-type substrate 10 has disposed thereon an N+ region 11 and an N-type epitaxial layer 12. A P-type region 13 is diffused into the layer 12 and an N-type region 14 is diffused into the region 13. An isolation region 15 is formed by oxidizing the epi layer 12. This isolation region 15 is made to extend into the substrate 10. The formation of this isolation region 15, causes an N-type skin therein to be created at its interface 16 with epi layer 12. This skin creates an N-type channel 17 past the P-type region 13, so as to interconnect the N-type region 12 and the N-type region 14. Voltage applied to the P-type region 13 can cause this channel 17 to be pinched off.

Thus there is created a device which is a standard NPN bipolar transistor 18 in parallel with a junction FET 19. This is shown schematically in Fig. 2, where the N-type region 14 is the emitter of the bipolar transistor 18 and also serves as the source of the FET device 19, the P-type region 13 serves as both the gate of the FET 19 and the base region of bipolar transistor 18. The epitaxial layer 12 not only serves as the collector of the bipolar device 18 but also are the drain of the FET 19. The FET so created need only have the gate 13 and the source 14 externally connected. The dra...