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Complementary Field Effect Transistor High Density Decoder

IP.com Disclosure Number: IPCOM000078652D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kenyon, R: AUTHOR [+3]

Abstract

This is a decoder scheme in which the devices are complemented in the tree configuration, so that the true-complement generator usually found with decoders can be eliminated.

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Complementary Field Effect Transistor High Density Decoder

This is a decoder scheme in which the devices are complemented in the tree configuration, so that the true-complement generator usually found with decoders can be eliminated.

The high density complementary metal-oxide semiconductor (MOS) decoder, shown in the figure, is basically a series field-effect transistor (FET) decoder. Outputs 10 to 17 are connected to word lines attached to associated array cells and act as a node capacitance. For a selected set of address signals, A, B, C, D, only one path will turn on, thereby charging a single word line. For example, when input A is negative, B positive, C negative and D positive, then output 12 is selected. When for example, A is positive, B positive, C negative and D positive, then output 16 is selected.

The described decode scheme can be easily laid out, and results in a minimal number of devices and convenient access to each address line. by duplicating the circuit the complement of signal D can be used. The described decoder requires only one address line to be processed on chip, rather than having all address lines going through true-complement generators. Because devices are shared, the decode may be so laid out that its series resistance approaches twice that of a one-by-one device.

Furthermore, the only word line capacitance charged is the one selected, therefore, the standby power is reduced.

The actual on chip D line and complement D line can have t...