Browse Prior Art Database

Ferroelectric FET Device

IP.com Disclosure Number: IPCOM000078653D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Arnett, P: AUTHOR

Abstract

A nonvolatile low-voltage high-speed read/write semiconductor type memory cell is described. The field-effect transistor (FET) of the figure utilizes a four-layer gate structure 11 disposed on the surface 12 of a silicon substrate 10, into which source and drain diffusions 14 and 15 are made. The gate structure disposed over the channel region 13 between the source and drain diffusions consists of a layer of silicon dioxide 16 approximately 20 angstroms thick, overcoated with a layer of trap material 17 such as silicon nitride about 10 to 100 angstroms in thickness, over which there is deposited a ferroelectric material 18 such as 1000 angstroms of barium titanate and a metal gate electrode 19. Metal electrode 19 serves as a control gate.

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Ferroelectric FET Device

A nonvolatile low-voltage high-speed read/write semiconductor type memory cell is described. The field-effect transistor (FET) of the figure utilizes a four- layer gate structure 11 disposed on the surface 12 of a silicon substrate 10, into which source and drain diffusions 14 and 15 are made. The gate structure disposed over the channel region 13 between the source and drain diffusions consists of a layer of silicon dioxide 16 approximately 20 angstroms thick, overcoated with a layer of trap material 17 such as silicon nitride about 10 to 100 angstroms in thickness, over which there is deposited a ferroelectric material 18 such as 1000 angstroms of barium titanate and a metal gate electrode 19. Metal electrode 19 serves as a control gate.

The ferroelectric material 18 is used to provide a high-capacitance material between the gate electrode 19 and the trap material 17. The trap material 17 contains a high density of trap states for electrons which are spatially distributed, and whose energies preferably occur within the main gap of the semiconductor material. The oxide 16 guarantees a low density of semiconductor surface states and presents a potential barrier to charge leaving the trap material.

The FET described has two states or threshold voltages that are determined by the presence or absence of charge in the trap state. In the 0N state the free charge in the trap material comprises electrons, and in the OFF state the free charge in...