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Fabrication Process for Field Shield Devices

IP.com Disclosure Number: IPCOM000078667D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Yu, HN: AUTHOR

Abstract

Where field shields are used in the field-effect transistor environment, short circuits between the field shield and an adjacent gate electrode often occur, due to thin insulation between the field-shield elements and the gate electrode. The following fabrication process eliminates such shorting problems. The fabrication steps should be considered in conjunction with Figs. 1A, 1B, and 1C which are front, top, and side views, respectively, of a partially fabricated field-effect transistor.

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Fabrication Process for Field Shield Devices

Where field shields are used in the field-effect transistor environment, short circuits between the field shield and an adjacent gate electrode often occur, due to thin insulation between the field-shield elements and the gate electrode. The following fabrication process eliminates such shorting problems. The fabrication steps should be considered in conjunction with Figs. 1A, 1B, and 1C which are front, top, and side views, respectively, of a partially fabricated field-effect transistor.

Step 1) Thermally grow a thin layer of silicon dioxide on a p-type silicon substrate.

Step 2) Deposit a silicon nitride layer on top of the silicon dioxide layer.

The first two steps fabricate what is ultimately the gate insulation of the fabricated field-effect transistor.

Step 3) Deposit doped polycrystalline silicon on top of the silicon nitride and silicon dioxide layers.

Step 4) Thermally grow silicon dioxide or deposit a suitable glass on top of the polysilicon layer.

Step 5) Delineate and etch a device area using photolithographic masking and etching techniques. In this step, the silicon dioxide or glass layer and the polycrystalline silicon layer are etched down to the silicon nitride, which acts as an etch stop producing the device area shown in Fig. 1B. This step exposes the edge of the polycrystalline silicon field-shield element. Unless this area is insulated, a subsequently deposited polysilicon gate as shown in Figs. 1A,...