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Aluminum Silicon Self Aligned Gate Process With Field Shield

IP.com Disclosure Number: IPCOM000078668D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

The process shown in the accompanying figures permits the fabrication of metal-oxide-semiconductor field-effect devices, with either aluminum or silicon self-aligned gate devices. In addition, a field shield over the field oxide areas is provided, thus eliminating the possibility of forming parasitic devices and reducing leakage. The field shield is self-aligned to the device and diffusion areas. Referring to Fig. 1, the following steps are shown: 1) Grow a thin layer of silicon oxide over the entire surface of the semiconductor wafer. 2) Deposit a thin silicon nitride layer over the entire wafer.

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Aluminum Silicon Self Aligned Gate Process With Field Shield

The process shown in the accompanying figures permits the fabrication of metal-oxide-semiconductor field-effect devices, with either aluminum or silicon self-aligned gate devices. In addition, a field shield over the field oxide areas is provided, thus eliminating the possibility of forming parasitic devices and reducing leakage. The field shield is self-aligned to the device and diffusion areas. Referring to Fig. 1, the following steps are shown:
1) Grow a thin layer of silicon oxide over the

entire surface of the semiconductor wafer.
2) Deposit a thin silicon nitride layer over the

entire wafer.

Steps 1 and 2 form the gate insulator and the thin insulator under a subsequently formed field shield.
3) Deposit a layer of polycrystalline silicon over

the entire wafer.
4) Diffuse the polycrystalline silicon with an

appropriate dopant to render it conductive.

The following steps relate to the configuration shown in Fig.
2.
5) Open diffusion, gate, and charge-coupled device (CCD)

well areas in the polysilicon layer, etching down to

but not through the silicon nitride layer. A hot

mixture of ethylene diamine, pyrocatechol, and water,

can be utilized to etch the polycrystalline silicon

regions. (Mask Step 1)
6) Thermally oxidize the polycrystalline silicon layer.

This provides edge cover for the etched edges of

the polysilicon layer.
7) Deposit a second layer of polycrystalline silicon.
8) Pattern the second polycrystalline silicon layer,

to form a polysilicon crystalline gate and

interconnection areas.

(Mask Step 2)
9) Remove silicon nitride from source and drain diffusion

areas and dip etch, to remove thin oxide layer from

diffusion areas.

(Mask Step 3)
10) Diffuse source and drain polycrystalline gate and

interconnection areas with appropriate dopants;

simultaneously regrow a thick oxide in the diffusion

regions.

The following steps provide the arrangement shown in Fig. 3. 11)...