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Low Power Flip Flop Storage Cell

IP.com Disclosure Number: IPCOM000078676D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

This flip-flop consists of two cross-coupled transistors, the load elements of which are designed as constant-current sources. With the flip-flop in integrated technology the constant-current sources consist of reverse-biased Schottky diodes, in order to reduce the surface requirements.

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Low Power Flip Flop Storage Cell

This flip-flop consists of two cross-coupled transistors, the load elements of which are designed as constant-current sources. With the flip-flop in integrated technology the constant-current sources consist of reverse-biased Schottky diodes, in order to reduce the surface requirements.

The equivalent electric circuit diagram comprises two cross-coupled flip-flop transistors T1 and T2, with reverse-biased Schottky diodes D1 and D2 as load elements. The two diodes must be capable of supplying both the base current of the conductive transistor and the leakage current flowing into the collector of the blocked transistor. To ensure low, power dissipation, the current supplied must be sufficiently low.

These requirements are met by the Schottky contact arranged on a P base region. A schematic plan view of the layout is shown in Fig. 2. The two connected N emitters of T1 and T2 consist of the common N region. The two high-resistivity P base regions of T1 and T2 are embedded in this N region. Each P base region comprises an N+ collector region and a P+ base contact zone. The collector of one transistor and the base of the other are cross coupled through conductive connections L1 and L2.

Schottky contacts K1, K2 of suitable metal are applied to each P base region. Contacts K1, K2 form the reverse-biased diodes D1 and D2 and are jointly linked with the positive operating voltage +V.

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