Browse Prior Art Database

Associative Storage Cell

IP.com Disclosure Number: IPCOM000078677D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

This is an associative storage cell, whereby during searching the magnitude of the mismatch signal in the word sense line remains unaffected, irrespective of whether the searched word deviates from the reference word by one or several positions.

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Associative Storage Cell

This is an associative storage cell, whereby during searching the magnitude of the mismatch signal in the word sense line remains unaffected, irrespective of whether the searched word deviates from the reference word by one or several positions.

Only one of the cells belonging to a word is shown. This cell consists of a cross-coupled transistor flip-flop T1, T2 with load elements L1, L2. All cells of a word are linked in parallel in between upper word line W1 and lower word line W2. Upper word line W1, concurrently forming the word sense line, is connected to one pole (+V) via series resistor RW1, whereas lower word line W2 is linked with the other pole (ground) of the operating voltage source via series resistor RW2. In lieu of resistors RW1 or RW2 other current supply means can be used. The coupling points of the flip-flops are in each case connected to the base of read/write transistors T3, T4. The emitters of T3, T4 are connected to associated bit lines B0, B1. The collectors of T3, T4 are linked with the common connection of the load elements and word sense line W1.

In the quiescent state operating current I, generating a particular voltage drop on RW2, is impressed into all memory cells of a word line pair W1, W2. Assume a 1 is stored in the cell as shown, with T1 being conductive and T2 being blocked. All bit lines B0, B1 of the word cells are positively biased, so that read/write transistors T3, T4 of all cells are blocked.

During...