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Arrangement for Minimized Functional Test of LSI Logic Chips

IP.com Disclosure Number: IPCOM000078678D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

The arrangement allows a large scale integrated (LSI) chip with logic circuits to be fully function-tested with a minimum amount of testing effort, by limiting the test cases to "direct feed-through relationships" (DFR's) on the chip. A DFR is a relationship between an output and one of its related inputs, whereby the output is inverted (in phase or antiphase) as the input is inverted, while all the other inputs remain unchanged. It can be shown that such a DFR always exists between an output and each of its related inputs, that such DFR's represent the worst-case conditions of test in most circuit technologies and that, given the Boolean expression for the output as a function of its related inputs, the relevant DFR's can be calculated and listed by a computer program.

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Arrangement for Minimized Functional Test of LSI Logic Chips

The arrangement allows a large scale integrated (LSI) chip with logic circuits to be fully function-tested with a minimum amount of testing effort, by limiting the test cases to "direct feed-through relationships" (DFR's) on the chip. A DFR is a relationship between an output and one of its related inputs, whereby the output is inverted (in phase or antiphase) as the input is inverted, while all the other inputs remain unchanged. It can be shown that such a DFR always exists between an output and each of its related inputs, that such DFR's represent the worst-case conditions of test in most circuit technologies and that, given the Boolean expression for the output as a function of its related inputs, the relevant DFR's can be calculated and listed by a computer program. The collection of all the DFR's on a chip gives a "logical function description array" (LFDA). Testing based on this LFDA constitutes, therefore, the full and minimized functional test of the chip.

For a chip with N inputs (I0 to IN-1) and M outputs (00 to 0M-1), an entry in the LFDA consists of (2N+2) items. These are: (m; q0, s0, q1, s1,... qN-1, sN-1; p) Where m is the output pad address, qn (with n = 0, 1,... N-1) are the values ("0" or "1") of the inputs, sn are "switching parameters" for the inputs, and p is the polarity value (0 or 1) of the output expected

at the output pad m when the inputs are assigned values qn (n = 0,... N-1), as specified.

A switching parameter s of 1 is indicative of a DFR being tested. Its introduction in the LFDA entries allows multiple DFR's to be combined into one LFDA entry. For inputs which are not functionally related to the output, the qn values in the entries for that output can be set arbitrarily to 0.

Based on this LFDA chip definition, the arrangement (shown in Fig. 1) for testing chip 1 consists of an input switching network (ISN) 2, an output switching network (0SN) 3, and a compare circuit (CC) 4. Of an LFDA entry, read out from a store, not shown, the qn an sn values are fed into ISN 2, the address m going to OSN 3, and the p bit to CC 4. The ISN 2 comprises a ring-shift register 5 with N stages, a column of AND circuits 6 and a column of XOR circuits 7. On reading out an LFDA entry, register 5 is set to contain a 1 in its first stage. The AND circuits receive the outputs o...