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Browse Prior Art Database

Vertical Diode Capacitor Memory Cells

IP.com Disclosure Number: IPCOM000078690D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR [+4]

Abstract

This cell structures provide a very high-density memory array on the surface of a semiconductor substrate. Each cell includes essentially a diode serially connected to a storage capacitor, with the capacitor overlying the diode.

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Vertical Diode Capacitor Memory Cells

This cell structures provide a very high-density memory array on the surface of a semiconductor substrate. Each cell includes essentially a diode serially connected to a storage capacitor, with the capacitor overlying the diode.

In Fig. 1 the cell is shown as having a PN junction diode 10 formed in semiconductor substrate 12. The P region of the diode 10 is used as the bit/sense line 13 for the memory array. A layer of insulation 14, e. g., silicon dioxide, having a thin region 16 is disposed over the substrate 12. The thin region 16 is the dielectric of storage capacitor 18 having the N region of diode 10 as one electrode and a metal layer 20, e. g., aluminum, as the other electrode of the capacitor. The metal layer or electrode 20 is used as the word line for the memory array. The breakdown or avalanche voltage of the PN junction may be 18 volts, and a potential difference of 6 volts across the capacitor 18 may define a "1" bit of information and a zero potential difference may define a "0" bit of information.

The pulse program indicated in Fig. 2 describes two complete read-clear- write cycles of operating the cell of Fig. 1. At standby conditions, the word line or electrode 20 is biased at 6 volts and the bit/sense line 13 or P region is at zero volts. Therefore, at standby, when a 1 bit is stored in the cell, the potential difference across the cell with respect to the bit/sense line 13 is 12 volts and with respect to the word line 6 volts. Similarly, when a 0 bit is stored in the cell, the potential difference across the cell is 6 volts and zero volts with respect to the bit/sense line 13 and word line 20, respectively.

In the operation of the cell, when reading, the bit/sense line 13 is raised from zero volts to 6 volts and the word line 20 is lowered to zero volts. If no current flows in the bit/sense line a 1 bit of information is detected, but if current does flow a 0 bit is sensed. After the read operation when a 0 bit has been sensed, the information has been destroyed and, therefore, must be rewritten into the cell. Since the 0 bit is generally transferred to a latch attached to the bit/sense line 13, the information is simply written back during the next write operation.

To clear the cell before a write operation, the potential of the word line 20 is raised to 18 volts, or raised to 12 volts and the bit/sense line 13 lowered to -6 volts, to avalanche breakdown the d...