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NDRO Memory Cell Employing a Single Josephson Tunnelling Gate

IP.com Disclosure Number: IPCOM000078699D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Henkels, W: AUTHOR

Abstract

The drawing shows a memory cell using a single Josephson tunneling device J1 as a write gate in a superconducting loop, generally designated by numeral 10. Loop 10 has a first portion 10A comprised of two legs of the loop including Josephson device J1, while the second portion 10B is comprised of the other two legs of the loop. Portions 10A and 10B are arranged such that the inductance of each is the same. A current I(W)flows into and out of loop 10, depending upon the operations desired for the cell. The state of device J1 is determined by current I(b) flowing in line 12. Located underneath leg 10B is a line 14 having Josephson device J2 therein. J2 is a sense gate for detecting current flow through loop 10.

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NDRO Memory Cell Employing a Single Josephson Tunnelling Gate

The drawing shows a memory cell using a single Josephson tunneling device J1 as a write gate in a superconducting loop, generally designated by numeral 10. Loop 10 has a first portion 10A comprised of two legs of the loop including Josephson device J1, while the second portion 10B is comprised of the other two legs of the loop. Portions 10A and 10B are arranged such that the inductance of each is the same. A current I(W)flows into and out of loop 10, depending upon the operations desired for the cell. The state of device J1 is determined by current I(b) flowing in line 12. Located underneath leg 10B is a line 14 having Josephson device J2 therein. J2 is a sense gate for detecting current flow through loop 10.

Memory is accomplished in the cell by the generation of clockwise or counterclockwise superconducting persistent currents, representing the "0" and "1" states, respectively. Write gate J1 switches to a resistive state, when either a large positive or negative current I through it coincides with a pulse in bit line 12. This causes a redirection of current to portion 10B of the loop. The write gate automatically resets to its superconducting state when redistribution of current is accomplished. Application of a bit pulse I(b) when a small current (or zero current) exists through the gate device, does not cause gate J1 to switch. Consequently, no redistribution of current results in this case. The wr...