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Electrically Erasable FAMOS Memory Cell

IP.com Disclosure Number: IPCOM000078709D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Chang, CS: AUTHOR [+2]

Abstract

Electrical erasure of a floating-gate avalanche-injection metal-oxide-semiconductor (FAMOS) device is achieved, by the provision of an extra pair of junctions within the source or drain region of the FAMOS device. The extra junctions are at least partially covered by the floating gate and are biased during erasure, so that hot carriers are generated for discharging the floating gate.

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Electrically Erasable FAMOS Memory Cell

Electrical erasure of a floating-gate avalanche-injection metal-oxide- semiconductor (FAMOS) device is achieved, by the provision of an extra pair of junctions within the source or drain region of the FAMOS device. The extra junctions are at least partially covered by the floating gate and are biased during erasure, so that hot carriers are generated for discharging the floating gate.

Fig. 1 depicts a conventional FAMOS device comprising P-type diffusions D1, D2 and D3 in an N-type substrate 1. The diffusion D1 and the gate G1 serve as the X and Y select electrodes. G2 is the floating gate. The read and write operation of the conventional FAMOS cell of Fig. 1 are well understood.

Floating gate G2 is charged by electron injection under the biasing conditions, in which diffusion D2 undergoes avalanche breakdown. Erasure of the resulting negative charge on floating gate G2 is achieved, by providing a pair of N-type diffusions E1 and E2 within P-type diffused area D2, as shown in Fig.
2. It will be noted that floating gate G2 overlaps diffusions E1 and E2 to form an N-channel field-effect transistor (FET) within the P-type diffused area D2.

E1 is electrically connected to D2. Contacts are provided on E1 and E2 for the application of erasing bias voltages. In the "erase" operation, a negative voltage pulse is applied to E1 and a positive pulse to E2. Prior to erasure, the floating gate G2 is at some negative potential with respe...