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Browse Prior Art Database

Fast Adder for Multinumber Addition

IP.com Disclosure Number: IPCOM000078719D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR

Abstract

The figure shows a circuit schematic for an adder capable of handling a 16-number addition; however, it is readily extended to a 32-number addition. The outputs from the four input X and Y decoders 10 and 12, respectively, are "wire-ORed", at 14 for example, and fed to a 5 x 5 array. The arrays comprise a plurality of conventional duplicated current switch emitter-follower circuits, one of which is enclosed by block 16. The collector of these transistors at their respective cross-points are outputted through emitter-followers, e.g., transistor 17. These outputs are logical OR's by weight 0, 1, 2 --- 8. As shown, all the outputs form the array with equal weights and are wire-ORed, so as to provide the total OR combinations of all 8-tuples according to weight 0, 1 --- 8.

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Fast Adder for Multinumber Addition

The figure shows a circuit schematic for an adder capable of handling a 16- number addition; however, it is readily extended to a 32-number addition. The outputs from the four input X and Y decoders 10 and 12, respectively, are "wire- ORed", at 14 for example, and fed to a 5 x 5 array. The arrays comprise a plurality of conventional duplicated current switch emitter-follower circuits, one of which is enclosed by block 16. The collector of these transistors at their respective cross-points are outputted through emitter-followers, e.g., transistor
17. These outputs are logical OR's by weight 0, 1, 2 --- 8. As shown, all the outputs form the array with equal weights and are wire-ORed, so as to provide the total OR combinations of all 8-tuples according to weight 0, 1 --- 8. The identical scheme is repeated for 9 x 9 arrays, and the subadder will provide all the OR combinations of 16-tuples with a weight of 0, 1 --- 16.

For a 16-number subadder, two sets of 0 to 8 weighted ORed outputs in X and Y directions are fed to four sets of 9 x 9 arrays. The four 9 x 9 arrays provide S(0), C(0)/1/, C(0)/2/ and C(0)/3/ outputs in terms of the sub-adder. The C(0)/4/ output is obtainable from a two input conventional AND gate, not shown, whose inputs are weighted 8 and 8. The X and Y decoders 10 and 12 accommodate the inputs A(0) --- A(7). The inputs A(8) --- A(15) are implemented by decoder and current switch emitter-follower circuitry, schema...