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AC Stable Random Access Memory Cell

IP.com Disclosure Number: IPCOM000078723D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Arzubi, LM: AUTHOR

Abstract

This memory cell is capable of automatically regenerating stored data without requiring a separate addressing cycle. The circuit consists of four field-effect transistor (FET) devices and two capacitors. External lines, as shown in Fig. 1, include input-output data line (I/O), word line (W/L) and energy recovery line (ER). The circuit operates as follows. In order to write a "1" the I/O line and the W/L line are brought to a high potential while ER is kept grounded, so that devices Q1 and Q2 are turned on and C1 is charged. After a period of time in a "standby" mode the charge of C1 will tend to leak off, due to device leakage currents and must be restored. Fig. 2 shows the data pulses required in order to restore the charge on C1.

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AC Stable Random Access Memory Cell

This memory cell is capable of automatically regenerating stored data without requiring a separate addressing cycle. The circuit consists of four field- effect transistor (FET) devices and two capacitors. External lines, as shown in Fig. 1, include input-output data line (I/O), word line (W/L) and energy recovery line (ER). The circuit operates as follows. In order to write a "1" the I/O line and the W/L line are brought to a high potential while ER is kept grounded, so that devices Q1 and Q2 are turned on and C1 is charged. After a period of time in a "standby" mode the charge of C1 will tend to leak off, due to device leakage currents and must be restored. Fig. 2 shows the data pulses required in order to restore the charge on C1.

While all cells in a particular word line are unselected, ER is brought to a high potential and since C1 has been charged, Q2 will be turned on and the ER potential will appear at node B. Q3 will be turned on and C2 will be charged. When ER is thereafter grounded, the potential at node A will decrease in the amount that ER was up and, therefore, Q4 will turn on and C2 will transfer its charge to C1 through Q4. In order to read a 1, the cell is selected in the normal manner and energy on C1 will be transferred through Q1 to the I/O line. Writing a "0" is executed by grounding the I/O line so that C1 and C2 are both discharged. Since C1 is discharged, Q1 will not turn on at the time when ER goes, posi...