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LSI Continuous System Simulation

IP.com Disclosure Number: IPCOM000078738D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

McCullough, JW: AUTHOR [+3]

Abstract

A simulation program simulates dynamic performance of a large set of arbitrarily interconnected circuits, taking into account physical layout, packaging characteristics, process parameters, and other environmental parameters. The large-scale integration (LSI) circuit designer examines the simulation results to determine if redesign is necessary, or if the design is adequate to initiate fabrication of the LSI circuitry.

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LSI Continuous System Simulation

A simulation program simulates dynamic performance of a large set of arbitrarily interconnected circuits, taking into account physical layout, packaging characteristics, process parameters, and other environmental parameters. The large-scale integration (LSI) circuit designer examines the simulation results to determine if redesign is necessary, or if the design is adequate to initiate fabrication of the LSI circuitry.

The LSI design description contained in block 10, Fig. 1, is processed by block 15, using LSI simulation library information of block 20 to develop the simulation data base of block 25. Block 15 uses well-known small signal circuit analysis techniques to develop equivalent circuits and net lists describing the LSI logic to be simulated. The output of block 15 provides the simulation data base 25, formatted for efficient processing by the simulation algorithm of block 30. The prepared forcing patterns of block 35 are external inputs, in terms of voltage levels and times at which they are applied to the LSI logic. The simulation algorithm of block 30 applies the forcing patterns against the LSI logic to develop simulated responses or results, which are stored in all events file (AEF).

The simulation time is divided into discrete steps. The simulation algorithm of block 30 treats the individual LSI logic circuits independently during a time step, because the time step is small compared to circuit transition times. However, during any one time step, only those circuits which might have a change in a state variable are simulated. Those circuits clearly quiescent are not simulated. The computation of the circuit response for all of the individual logic circuits, is performed serially by circuit for a single time step. Inputs to all circuits make use of the results just computed and any external signal changes during the time step. After all circuits have been analyzed, the results are placed in the all events file 50 and time is incremented. The procedure just described and shown in Fig. 2, is repeated until the simulation time is completed.

In Fig. 2, the first step is to initialize inputs, state variables and activity. This step is represented by block 31. The operation then steps to the first circuit which may be simulated. The simulation data base 25 sets forth the sequence for processing the individual circuits of the LSI circuits. A determination is then made as to whether or not the first circuit is active. This determination is represented by decision block 33 in Fig. 2. The activity determination algorithm is shown in Fig. 3.

Activity information stored for each circuit includes a self-activity indicator, a summary input change indicator, input signal logic level indicators, and a logic level of this circuit's own output. All circuits are simulated for the first step of a simulation run, by forcing the self-activity indicator on.

Thereafter, an activity determination is made for e...