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High Performance DC Motor Servomechanism

IP.com Disclosure Number: IPCOM000078746D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Valent, JA: AUTHOR

Abstract

This hybrid digital-analog proportional-plus-integral motor servo-mechanism provides bidirectional acceleration from rest to a steady-state speed, followed by a controlled-speed running interval, by a speed-servo. Subsequently, upon a command to stop the motor the motor is brought to rest at a command stop-position by a position-servo.

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High Performance DC Motor Servomechanism

This hybrid digital-analog proportional-plus-integral motor servo-mechanism provides bidirectional acceleration from rest to a steady-state speed, followed by a controlled-speed running interval, by a speed-servo. Subsequently, upon a command to stop the motor the motor is brought to rest at a command stop- position by a position-servo.

The mode of operation of the servo is controlled by switch 10. This switch is shown in the speed-mode state, the alternate state being the position-mode. In the speed-mode, feed-forward signal 11 supplies a steady-state analog signal to summing junction 12, which is calculated to cause operational amplifier 13 and class-A power amplifier 14 to energize DC high torque - low inertia motor 15 in a manner to produce substantially the desired motor speed, if all parameters of the system are at nominal values.

This motor drives load 16 and digital tachometer 17. This tachometer supplies 90 degrees phase shifted output signals on conductors 18 and 19. The phase relationship of these signals is decoded by network 20 to provide a motor direction output on conductor 21. Each pulse of either or both of these signals is decoded to provide motor distance output pulses on conductor 22.

The signal on conductor 18 is applied to a motor-speed-determining network
23. In this network, a counter 24 counts the number of cycles of oscillator 25 which occurs between consecutive pulses on conductor 18. The count in counter 24 at the occurrence of a pulse is compared to reference count 26, and a binary speed-error number is generated for that tachometer period at conductor 27.

This speed-error number is applied to register 28 and digital-to-analog converter 29. At each tachometer pulse, the speed-error number is recomputed. Between pulses, the number in the register causes an analog voltage to be applied to the summing junction 12, via filter 30 and conductor 31, to modify the feed-forward voltage and thereby adjust the motor speed to the desired value, as determined by the reference count.

During the speed-mode the speed error is integrated using digital techniques. The speed-error number is applied to bidire...