Browse Prior Art Database

Variable or Fixed Field Length Cam Shift Register Memory with Data Compaction

IP.com Disclosure Number: IPCOM000078750D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Cordi, VA: AUTHOR [+3]

Abstract

In content- addressable memories (CAM), a word or data record is specified by stating the value of part of its contents. The memory may return no value, a single value or several values.

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Variable or Fixed Field Length Cam Shift Register Memory with Data Compaction

In content- addressable memories (CAM), a word or data record is specified by stating the value of part of its contents. The memory may return no value, a single value or several values.

There are numerous applications for content-addressable memories, e.g. as a directory for a memory in a memory hierarchy. A virtual address is presented to the shift register memory; and, if the page of data exists at that level, the output of the shift register memory is the physical address of the page in memory.

Sorting is another part of many large business data-processing problems. The shift register memory described can be considered to be a random file of data records, with the capability of producing a completely ordered file.

Bipolar CAM's with fast access, limited data width and high cost be organized as CAM's, with large capacity, slow speed and low cost exist at the low end of the technology spectrum. This publication, which employs shift register memories with data compaction capability, fills the gap in CAM technology - medium cost-medium performance.

When some of the data in a shift register memory is read out and not recycled, blanks are created, and the remaining data may no longer be contiguous. This can occur in a content addressable memory, if the data is not processed on a "first-in first-out" basis, i.e., records may be written, read with recycling, or read without recycling, in an arbitrary order. If in addition to being processed in arbitrary order the records are of variable length, it becomes imperative that data be contiguous if full memory utilization is to be achieved. Described is a technique for compacting data into contiguous form in shift register memories.

Tables 1 and 2 are illustrations of the data format of two records in the shift register memory before and after compaction, respectively.

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The figure shows a serial shift register memory m...