Browse Prior Art Database

Highly Wire Bondable Low Failure Exposure Top Surface Metallurgy

IP.com Disclosure Number: IPCOM000078760D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Fraser, HR: AUTHOR [+3]

Abstract

This technique provides an improved top surface metallurgy particularly suitable for wire bonded pads, by improving the quality and integrity of the bond, increasing the metal-metal and metal-glass adhesion, and by supplying a bonding area which possesses uniform stress distribution.

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Highly Wire Bondable Low Failure Exposure Top Surface Metallurgy

This technique provides an improved top surface metallurgy particularly suitable for wire bonded pads, by improving the quality and integrity of the bond, increasing the metal-metal and metal-glass adhesion, and by supplying a bonding area which possesses uniform stress distribution.

Either by evaporating or plating, a chrome layer 10, a copper layer 12, a nickel layer 14, and a gold layer 16 are deposited upon a glass substrate 18, Fig.
1. Next, the structure is heat treated at a temperature of between 400 degrees C and 810 degrees C for approximately one hour. This heat treatment causes intrinsic stress relief in the copper, nickel, and probably the chromium so as to provide an ideal stress buffer or absorption layer. After the heat treatment or annealing step, there exists (Fig. 2) a chrome-glass diffusion boundary layer at 20, a chrome-copper grain boundary diffusion layer 22, a nickel-copper alloy boundary layer 24, and a nickel-gold alloy boundary layer 26. The nickel-gold eutectic is ideally suitable for the deposition of an additional gold layer 30, Fig. 3. The annealing of chrome region 32, copper region 34, and nickel region 36 relieves the overall package stress. Selective etching according to conventional photoresist techniques removes the metals at the regions 38 and 40, so as to define a chip and wire bonding area 42 suitable for joining a semiconductor, schematically shown at 44 via w...