Browse Prior Art Database

FET Integrated Circuit Having Two Polysilicon Layers

IP.com Disclosure Number: IPCOM000078762D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR

Abstract

A single doped polysilicon layer has been proposed for shielding the field oxide region (nondevice areas) of field-effect transistor (FET) integrated circuit devices, as well as for forming the FET gate electrodes. However, where only one polysilicon layer is used, the polysilicon FET gate electrode material cannot be used as a gate interconnection layer which is electrically insulated from and crosses over the polysilicon field shield.

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FET Integrated Circuit Having Two Polysilicon Layers

A single doped polysilicon layer has been proposed for shielding the field oxide region (nondevice areas) of field-effect transistor (FET) integrated circuit devices, as well as for forming the FET gate electrodes. However, where only one polysilicon layer is used, the polysilicon FET gate electrode material cannot be used as a gate interconnection layer which is electrically insulated from and crosses over the polysilicon field shield.

The doped polysilicon forming the FET gates can be employed also as a gate interconnection layer, by providing two separate doped polysilicon layers. One layer is used for the FET gate electrodes and the gate interconnection pathways (between the silicon gate FETs formed on the same chip), and the other layer is used for the field shield. This is achieved by growing an initial oxide 1 on silicon substrate 2 and depositing polysilicon layer 3 on oxide 1. The polysilicon layer is partially oxidized to yield oxide layer 4, as shown in Fig. 1. FET device windows are opened in layers 1, 3 and 4 and gate oxide layer 5, gate silicon nitride layer 6 and second polysilicon layer 7 are formed, as shown in Fig. 2.

The FET gate region is defined by etching through layers 5, 6 and 7 in the source and drain areas 8 and 9, and in the field region 10 where the second polysilicon layer 7 (to be used as the gate interconnection layer) is not desired. Source and drain 8 and 9 and polysilicon 7 are...