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Multilevel Interconnection Metallurgy System for Semiconductor Devices

IP.com Disclosure Number: IPCOM000078766D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Dalal, HM: AUTHOR [+2]

Abstract

This method and resulting structure reduces metal-to-metal resistance in small area contacts.

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Multilevel Interconnection Metallurgy System for Semiconductor Devices

This method and resulting structure reduces metal-to-metal resistance in small area contacts.

It is conventional in multilevel interconnection metallurgy systems to connect the various levels of the system through relatively small openings, commonly referred to as via holes. Via holes are opened through the passivation layer overlying the metallurgy layer. Subsequently, the top metallurgy layer is fabricated which contacts the lower level metallurgy level through the via hole. It has been observed that high-contact resistance between the metallurgy levels occurs, particularly when utilizing small via holes with a diameter less than one mil. One solution to reduce the resistances is to sinter the resultant metallurgy system at high temperatures on the order of 500 degrees C, in order to bring about interdiffusion. However, this high temperature degrades the aluminum to silicon contact. Also, emitter-base shorting may take place by aluminum penetration. Further, changes in grain structure may not be able to bring about interdiffusion, e.g. in refractory metals.

In this method, the basic concept is to provide a second metal between the adjacent metallurgy layers, at least in the contact areas. As illustrated, a first level of metallurgy 10 is deposited over dielectric layer 12 bonded to substrate
14. The second level metallurgy 16 contacts the lower level 10 through via hole
18. Providing an inte...