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AC Test Pattern Reduction

IP.com Disclosure Number: IPCOM000078771D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR

Abstract

This technique improves AC test pattern generation by eliminating invalid and redundant patterns prior to test generation.

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AC Test Pattern Reduction

This technique improves AC test pattern generation by eliminating invalid and redundant patterns prior to test generation.

In accordance with the present technique, rules are established to filter out invalid and redundant AC test patterns prior to generation. Previously, DC test patterns were converted into AC test patterns and used indiscriminately for AC testing. By the present rules, logic circuit blocks are first sorted out to determine the applicability of an AC test pattern. Each logic circuit block having either two or more inputs, or having all the inputs of the logic circuit block as primary inputs to the chip are sorted out and listed separately. The list of those logic circuit blocks with corresponding primary inputs are used to check against each given DC test pattern to perform screening. The following table summarizes all possible conditions a logic circuit block can have at its input: T:ABLE 1

NAND (AND) BLOCK NOR (OR) BLOCK

CASE I. All inputs are logic 1's. All inputs are logic 0's. CASE II. Only one logic 0 input, Only one logic 1 input, all other inputs are logic all other inputs are logic

1's. 0's.

CASE III. Two or more logic 0 Two or more logic 1 inputs. Other inputs may inputs. Other inputs may

be logic 1's, or no other be logic 0's, or no

inputs. other inputs.

By the present technique, three rules are established for each of the foregoing three cases as follows: Rule 1 - Exclusively for Case I.

"Only pulse one input of the logic circuit block - perference is given to the input which was not pulsed by previous valid...