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Random DC Functional Test Pattern Discriminator

IP.com Disclosure Number: IPCOM000078772D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR

Abstract

This is a technique for minimizing a random DC functional test pattern without software simulation for logic chip testing.

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Random DC Functional Test Pattern Discriminator

This is a technique for minimizing a random DC functional test pattern without software simulation for logic chip testing.

Refer to Fig. 1 for a random DC functional test pattern provided at the primary input of the logic chip, including three primary NAND logic blocks. The test pattern is in terms of logic 1's and 0's. Between any two adjacent patterns, there is only one input change (either a logic 1 or 0). By comparing the particular pattern (n) with its immediate predecessor (number n-1), the single input change may be located. These changes in each pattern have been enclosed in a square in the Fig. 1 illustration. From a given digitized logic chip description, it is easy to sort out the chip's primary inputs and their immediate connected logic blocks in the chip. A block is qualified as a primary logic block when all its inputs serve as primary inputs to the chip. Thus, each of the blocks shown in Fig. 1 are primary logic blocks. Once the single input change between two adjacent test patterns is located, the affected primary logic block(s) may be traced out from the list of primary logic blocks vs. primary inputs.

In DC stuck-fault theory, it is not desirable to have patterns to any one NAND block with two or more logic 0 inputs. Patterns of good quality should only consist of one logic 0 per input per pattern, and one additional pattern with logic 1's for all inputs. For a NAND circuit with two or more inputs, if the previous pattern (n-1) had a logic 0 input, and if the single input change in the present pattern (n) provided two or more logic 0's, then the present pattern will not cause any significant difference from the previous one. Hence, the present pattern is redundant and may be eliminated without effecting pattern sequence.

Similarly, if the previous pattern had two or more logic 0 inputs on a NAND primary block, and the single input change in the present pattern created one less logic 0 at the same logic block, then the previous pattern may be eliminated due to redundancy. It is so chosen because the pattern with the fewer logic 0 inputs is more likely to change into a meaningful pattern later. If the change from one test pattern to the next results in an input change to a pattern which effects two or more primary logic blocks, and if the predicted output of one of the affected primary blocks is to be changed due to the potential minimization, then the pattern is preserved. An example is shown in Fig. 3.

As circuit density increases in large-scale integrated circuit chips, the chances of having logic blocks with two or more inputs is much greater than single input blocks as primary circuit blocks. If it is assumed that all inputs have equal chances of having two or more 0 inputs occur at a HAND block, then for a two input block, chances are one in every four patterns, for a three input block it is four in eight patterns, while in a four input block it would be eleven...