Browse Prior Art Database

Priority Interrupt Queuing

IP.com Disclosure Number: IPCOM000078775D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Grant, CH: AUTHOR [+3]

Abstract

A channel scan feature is provided to search for queued interrupts on a subchannel basis during channel idle periods. The pending interrupt code is updated whenever a queued interrupt is found having an interrupt code, which is of higher priority than that of the pending interrupt. The channel interfaces with a processor (CPU), a storage control unit (SCU) and a plurality of I/O control units each control unit being either unshared to serve only one I/O device or shared to serve more than one I/O device. Each logical connection to a device is termed a subchannel and the connected subchannels may be either all unshared, all shared or a mixture of both types.

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Priority Interrupt Queuing

A channel scan feature is provided to search for queued interrupts on a subchannel basis during channel idle periods. The pending interrupt code is updated whenever a queued interrupt is found having an interrupt code, which is of higher priority than that of the pending interrupt. The channel interfaces with a processor (CPU), a storage control unit (SCU) and a plurality of I/O control units each control unit being either unshared to serve only one I/O device or shared to serve more than one I/O device. Each logical connection to a device is termed a subchannel and the connected subchannels may be either all unshared, all shared or a mixture of both types.

Included in the channel is a unit control word store (UCWS), which is used to buffer control information in the form of unit control words (UCW's). The UCWS is arranged into groups of UCW's, with each unshared subchannel requiring two contiguous UCW's of a group designated as words 0 and 1 having a format shown in Fig. 2, and each shared subchannel requiring three words of a group designated as words 0, 1 and 7, where the format of words 0 and 1 are identical with words 0 and 1 for the unshared subchannel and word 7 has a format as shown in Fig. 3. Subchannel addressing of UCWS is described in the IBM Technical Disclosure Bulletin Vol. 13, No. 8, Jan. 1971, Pages 2288 - 2290.

The channel, when it is idle, scans the UCW's in the UCWS for potential interrupts. If an interrupt request is pending, interrupt address buffer (IAB) and interrupt code buffer (ICB) hold the unit address (UA) and the interrupt code, indicating the type of interrupt, respectively, which are associated with the interrupt request. Backup interrupt address buffer (BIAB) holds the UA of the last interrupt, or the UA last used in a scan operation. The UA in BIAB is gated to the unit control word address register (UCWAR) and stepped by one to access the next UCW word 0 from the UCWS. The subchannel status (SCS) portion, bits 32 through 35, of the accessed UCW word 0 are gated to the SCS register. If the status decoder detects that an interrupt is pending, the code in the SCS register is compared with the code in the ICB. If the code in the SCS register has a higher priority, a set code sequence is initiated wherein the higher priority interrupt code presently in the SCS register is gated into the ICB, replacing the lower priority code and the address in UCWAR is transferred to IAB. If the code in the SCS register is of the same or less priority than that in ICB, the I:AB and ICB are not changed.

Following the set code sequence, in the case of an unshared subchannel, the address in the UCWAR is stepped by one. However, in the case of a shared subchannel, a UCW sequence is performed to fetch the UCW word 7, the unit address portion of whi...