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Addressing Combined Memories

IP.com Disclosure Number: IPCOM000078777D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Phelps, BE: AUTHOR

Abstract

Memories A, B, and C are combined so that only a fraction of each memory is utilized in a manner, such that the entire combination is addressed by contiguous memory addresses. The result is a combination of memories, which appears to the user to be one logical memory.

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Addressing Combined Memories

Memories A, B, and C are combined so that only a fraction of each memory is utilized in a manner, such that the entire combination is addressed by contiguous memory addresses. The result is a combination of memories, which appears to the user to be one logical memory.

Each memory contains sixteen-addressable locations (0 - 15). Memories A and C are 75% utilized, that is, twelve locations 0 - 11 are addressed. Memory B is 50% utilized, that is, eight locations 0 - 7 are addressed. Each memory is provided with a decoder which can decode up to four binary inputs, which will provide a maximum of sixteen outputs for selecting the sixteen memory locations. Addresses are presented to the memory system by address register 10, which stores a 4-bit binary address. A high-order address position is provided by block address register 12.

The table illustrates the memory selected, and the address selected within the memory for each sequential binary address stored in the address register and block address register 10, 12. For low-numbered addresses, the high-order bit positions 0 and 1 of address register 10 do not energize AND circuit 14. The output of AND circuit 14 is negative and is inverted by inverter 16, to thereby energize one leg of AND circuit 18. For low-order addresses, the block address register 12 contains a zero. The output 20 which is negative, is inverted by inverter 22. This energizes the other leg of AND circuit 18, thereby energizing the output SELECT A. This causes memory A to be selected for addresses 0 - 11. Binary address 12...