Browse Prior Art Database

Dynamic Configuration

IP.com Disclosure Number: IPCOM000078778D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

A memory array of multiple blocks of partially defective monolithic circuit chips, with redundant (spare) block capacity, is dynamically reconfigured to circumvent any faulty block. Spare block substitution is controlled by a counter and supplemental logic integrated, into the address translating network required for chip selection.

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Dynamic Configuration

A memory array of multiple blocks of partially defective monolithic circuit chips, with redundant (spare) block capacity, is dynamically reconfigured to circumvent any faulty block. Spare block substitution is controlled by a counter and supplemental logic integrated, into the address translating network required for chip selection.

Drawing A illustrates a basic module array composed of four partially (25%) defective chips. Chip storage capacity is 128 bits. Each chip of the module contains a differently situated defective quadrant of 32-bit capacity. Module capacity therefore is 384 bits (3/4 of 512). Address lines for coordinate bit selection in each chip are also shown.

An array card consisting of 24 such modules with addressing logic is shown in Drawing B. Drawing C illustrates logic for addressing 8192 nondefective bits, out of the capacity of 9216 nondefective bits of such cards, in blocks of 1024 bits. The dynamic reconfiguration logic is used to dynamically substitute the spare 1024 bits available in the card as a block for any of the eight normally used blocks, When failure occurs in the latter. Drawing D shows the dynamic reconfiguration logic.

The reconfiguration logic includes a four-stage counter (CTR) and a translation control network, effective to derive an 8-bit translation control code R (R/0/-R/8/) from the counter output. Application of the R code in the control of the address translation function of Drawing C, is detailed...