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Microcontroller for I/O Control Signals

IP.com Disclosure Number: IPCOM000078782D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Lewis, DO: AUTHOR [+3]

Abstract

A microcontroller provides I/O control signals at a rate of the I/O device it is controlling. The controller includes a random-access memory (RAM) for storing instructions containing a first group of data bits for determining which I/O control lines will be active, and a second group of data bits for determining when they will be active. The sequence and times for activating the I/O control lines are easily changed, by merely loading the RAM with new instructions. The clock of the I/O device being controlled drives a counter whose output is compared with the second group of bits and upon comparison, a gating signal is developed to bring up the control lines as determined by the first group of bits.

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Microcontroller for I/O Control Signals

A microcontroller provides I/O control signals at a rate of the I/O device it is controlling. The controller includes a random-access memory (RAM) for storing instructions containing a first group of data bits for determining which I/O control lines will be active, and a second group of data bits for determining when they will be active. The sequence and times for activating the I/O control lines are easily changed, by merely loading the RAM with new instructions. The clock of the I/O device being controlled drives a counter whose output is compared with the second group of bits and upon comparison, a gating signal is developed to bring up the control lines as determined by the first group of bits.

RAM 14 is loaded with sixteen-bit instructions via input bus 2, under control of a LOAD signal on conductor 1. The instructions are loaded at addresses determined by counter 12, whose output is gated by the LOAD signal via AND circuit 20 and OR circuit 22 to address RAM 14. Counter 12 is advanced by the LOAD signal. After RAM 14 has been loaded, instructions are read therefrom under control of a READ signal on conductor 3 at addresses determined by counter 13. The addresses are supplied to RAM 14, under control of the READ signal via AND circuit 21 and OR circuit 22. The addressed instruction is loaded into register 16 via output bus 4, under control of a START signal on conductor
15. Bits 0-3, 4-7 and 8-15 of the instructions ar...