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Shift Register

IP.com Disclosure Number: IPCOM000078788D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Denis, B: AUTHOR

Abstract

This shift register architecture provides high-speed shifting performance.

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Shift Register

This shift register architecture provides high-speed shifting performance.

The shift register comprises serially connected identical stages. Each one of the stages includes two inputs (R, S) driving inverter transistor circuits, and a direct coupled flip-flop using biemitter transistors. One emitter of each biemitter transistor is connected to a synchro input CK. When the input CK is set at binary "0" level, the stage output condition will not vary regardless of R and S levels. The stage is therefore in a "memory" state. When input CK is fed with a binary "1", the flip-flop state may be modified in accordance with the binary levels fed to R and S. The stage is thus said to be in a "write" state.

Two signals Phi and Phi are needed to perform the data shift in the register. The signal Phi is fed to even register stages (Qt, Qt+2, Qt+4 .....), while Phi is fed
to odd stages (Qt+1, Qt+3, Qt+5 .....).

In operation, while writing is performed into the first stage by setting Phi at 1, the next stage is set in memory state since Phi = 0. The inputs R, S of the next stage are preconditioned and that stage is ready to store the shifted information as soon as Phi = 1 ; and so on, the information is shifted by having M alternatively set at 0 and then a 1 level.

Such a design leads to a shift register performing two shifting operations within one single-clock period.

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