Browse Prior Art Database

Block Address Scheme Based on Associative Memory Blocks

IP.com Disclosure Number: IPCOM000078793D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Koch, K: AUTHOR

Abstract

This Block Addressing Scheme (BAS) is based on the fully associative addressing capabilities of the Memory Blocks (MBs), described in the IBM Technical Disclosure Bulletin, Vol. 15, No. 3, August 1972, pages 1035-1036, "Memory Addressing System".

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Block Address Scheme Based on Associative Memory Blocks

This Block Addressing Scheme (BAS) is based on the fully associative addressing capabilities of the Memory Blocks (MBs), described in the IBM Technical Disclosure Bulletin, Vol. 15, No. 3, August 1972, pages 1035-1036, "Memory Addressing System".

The BAS is applicable to systems having single or multiple linearly addressed byte spaces. Main memory is composed of a number of independent memory units (MUs), where each processor can access a number of MUs. Data in the system are organized in uniquely named segments of variable extents. Data references have the form segment identifier . offset, where segment identifier (segid) points to the addressed segment, and offset points to the addressed data within that segment. Each segment consists of two components indicated by the s b field, namely, a segment identifier component which contains segment identifiers and a byte component which contains data.

The segment identifier table (SIT) is attached to the processing units (PUs) and is associated with a single process. It contains one entry for each segment of the currently active process for which addressability is established.

In BAS a MU is divided into a number of MBs. Each MB has its own memory block descriptor (MBD) containing the MB-address(es) and status information about the segment block contained in the MB. For the MBD shown in the figure, it is assumed that the MB associated with it has a lower-bound and an upper- bound MB-address, where the segment identifier is separated from the MB- addresses. If a MB has the minimum addressing logic, the MBD contains only one MB-address.

For the flow of control of memory references in BAS, it is assumed that the authorization and s/b fields (top of figure) are set in the instruction decoding phase according to the instruction type.

In BAS all memory references consist of segid offset and s/b. The contents of the three offset subfields (index register, base register, and displacement) are sent to the offset computation unit, which computes the offset in the requested segment.

As offset computation is carried out, segid is compared with the segment identifiers contained in SIT. A match causes a read out of the authorization information and the MU number. The MU is then immediately addressed in the form of segid offset and s/b. Because SIT contains only one entry for each addressable segment of a particular process, it is a very small table. Thus, segid searches in SIT can be utilized at little extra time which is less than that for offset computation.

The authorization information is checked at the same time as MU addressing. A match does not cause action being taken. A mismatch leads to an

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authorization error being reported to the Supervisor. This operation must be fast enough to prevent data from being destroyed in the MU.

In case of an unsuccessf...