Browse Prior Art Database

Flip Chip Pad Relocation

IP.com Disclosure Number: IPCOM000078807D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Aimi, BR: AUTHOR

Abstract

This flip-chip solder pad relocation technique allows the use of larger integrated circuit chips, without decreasing reliability of a chip-to-substrate bonds. As previously reported by L. S. Goldman, (IBM Journal of Research and Development, May 1969, pages 251-265), the number of cycles to failure for flip-chip mounted semiconductor devices is inversely proportional to the square of the distance from the pads to the neutral point (N.P.) of the chip. By moving chip-to-substrate bonds closer to the neutral point without altering basic chip layout design, larger chips and/or more reliable bonds may be fabricated.

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Flip Chip Pad Relocation

This flip-chip solder pad relocation technique allows the use of larger integrated circuit chips, without decreasing reliability of a chip-to-substrate bonds. As previously reported by
L. S. Goldman, (IBM Journal of Research and Development, May 1969, pages 251-265), the number of cycles to failure for flip-chip mounted semiconductor devices is inversely proportional to the square of the distance from the pads to the neutral point (N.P.) of the chip. By moving chip-to-substrate bonds closer to the neutral point without altering basic chip layout design, larger chips and/or more reliable bonds may be fabricated.

Fig. 1 shows a plan view of a typical integrated circuit chip 3. Normally, chip mounting pads 4 are designed to lie in a peripheral region surrounding an array 5 of active semiconductor devices. Fig. 2 is a sectional view of a single modified pad location. After chip 3 has been fabricated, covered with a passivating layer 6 and via hole etched, conductive metallurgy 7 is applied, by a suitable technique, to form a new location for solder bump 8 at a point closer to the neutral point N.P. This technique allows optimum design and utilization of chip real estate, by allowing the via hole locations at the chip level to remain at the periphery of the circuit array, and to allow optimum pad size and location by placing them on top of a passivation layer and displaced closer to the neutral point. Optimization of substrate-ship pad interfa...