Browse Prior Art Database

Four Phase Dynamic Logic Buffer

IP.com Disclosure Number: IPCOM000078828D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Long, GB: AUTHOR

Abstract

The drawing shows a buffer circuit 20 which can be used in place of a padding capacitor 40, to provide current drawn by switching fieldeffect transistors 32 of a plurality of circuits 30 being driven, without reducing the voltage at node 38 to a value which is below the binary up level. Current is drawn by transistors 32, because the gate-to-drain and gate-to-source capacitances of devices 32 act as a charge storage divider with the wiring capacitance of the driving net connected to node 38.

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Four Phase Dynamic Logic Buffer

The drawing shows a buffer circuit 20 which can be used in place of a padding capacitor 40, to provide current drawn by switching fieldeffect transistors 32 of a plurality of circuits 30 being driven, without reducing the voltage at node 38 to a value which is below the binary up level. Current is drawn by transistors 32, because the gate-to-drain and gate-to-source capacitances of devices 32 act as a charge storage divider with the wiring capacitance of the driving net connected to node 38.

When a large number of circuits 30 are connected to a short wiring net, the current drawn to charge the gate-to-drain capacitances as the signal B goes from an up to a down level, can discharge the driving net wiring capacitance to a value less than the critical binary up level. Thin-oxide padding capacitors 40 are often added to alleviate this problem. The padding capacitors, however, reduce reliability by increasing the total thin-oxide area on a chip and also occupy a substantial amount of chip area. By removing wire 41 and capacitor 40 from the circuit and replacing them with wires 15 and 25, to connect buffer circuit 20 between driving circuit 10 and driven circuits 30, circuit reliability and density can be increased by a factor of 4 or 5 whenever the added power dissipation and logic inversion caused by buffer circuit 20 is acceptable.

Operation of the circuit commences when transistor 11 unconditionally charges node 28, causing transist...