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Browse Prior Art Database

3 Device Cell Dynamic Random Access Memory

IP.com Disclosure Number: IPCOM000078829D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Simi, VM: AUTHOR

Abstract

The higher cell densities which characterize the development pattern of memories creates additional difficulties in cell design. As the density increases the interaction between communicating cells and circuits is significant. The reason is that the ratio of the stored charge of the dynamic cell to the stray capacitance decreases. As this capacitance ratio decreases, the magnitude of the sense current decreases resulting in a lower signal-to-noise ratio. The configuration disclosed takes advantage of reduced area and power of the 3-device cell, but has the noise tolerance of a 6-device cell. Thus, more cells can be put on a chip for a given signal-to-noise ratio when differential sensing is used.

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3 Device Cell Dynamic Random Access Memory

The higher cell densities which characterize the development pattern of memories creates additional difficulties in cell design. As the density increases the interaction between communicating cells and circuits is significant. The reason is that the ratio of the stored charge of the dynamic cell to the stray capacitance decreases. As this capacitance ratio decreases, the magnitude of the sense current decreases resulting in a lower signal-to-noise ratio. The configuration disclosed takes advantage of reduced area and power of the 3- device cell, but has the noise tolerance of a 6-device cell. Thus, more cells can be put on a chip for a given signal-to-noise ratio when differential sensing is used.

The basic unit consists of a three-device N-channel field effect transistor (FET) memory cell, Fig. 1, that when time multiplexed with additional circuitry appears as an eight-device memory cell. The cell is of the dynamic type in that it must be refreshed periodically to retain the data. The method the cell is selected, written, and read is advantageous. The cell has the characteristic of being refreshed when read and with proper implementation, a large section of the memory array can be refreshed at one time. The noise tolerance of this configuration is enhanced, because of the differential mode in which the cell is written and read.

The operation of the memory, Fig. 2, is as follows:

I. To Write

A. Column select, row select and delayed row

select are brought high with reset low.

1) To write a "1", B1 is brought high and B0 low.

2) To write a "0", B1 is brought low and B0 high.

B. Data Input

1) Data is transferred thru Q8 and Q...