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Adaptive Delta Modulator With Variable Sample Rate

IP.com Disclosure Number: IPCOM000078830D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Jones, CK: AUTHOR [+2]

Abstract

A method is described which overcomes the slope overload problem of a delta modulator. Speech may be digitally recorded with an average bit rate less than 10K per second. One known way to overcome the slope overload problem, is to vary the step size according to the codes of the bits just preceding a particular step. Another way, is to vary the bit rate according to the code of the bit just preceding a given bit.

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Adaptive Delta Modulator With Variable Sample Rate

A method is described which overcomes the slope overload problem of a delta modulator. Speech may be digitally recorded with an average bit rate less than 10K per second. One known way to overcome the slope overload problem, is to vary the step size according to the codes of the bits just preceding a particular step. Another way, is to vary the bit rate according to the code of the bit just preceding a given bit.

The hardware required to generate variable-bit rates is shown in Fig. 1. Fig. 1 is a block diagram of a generalized adaptive delta modulator, in that both the step size and the threshold are varied with the bit stream. The step size and the threshold are varied two ways. The S and T blocks 1 and 2 are varied depending on the code state in the LS1, LS2, LS3, LS4, register 3; m from block 4 is increased or decreased depending on the code state in the LS1, LS2, LS3, LS4 register. Both the step size SK(o)K(s)/m/, and the threshold, TK(o)K(s)/m/, are varied when m is varied.

Referring to the timing diagram in Fig. 2, four clock pulses are generated. Normally only T0 is used. However, if three "1" bits appear in a row, a bit is generated by the next T2 pulse. With three 1 bits the bit rate is increased to overcome the slope overload condition. If the bit generated by the T2 pulse is a 1, the bit rate is further increased by generating a bit by the next T3 pulse. The 1 bit at T2 makes four 1 bits in a row. Note...