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High Speed Digital Sampler

IP.com Disclosure Number: IPCOM000078842D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Weiss, RL: AUTHOR

Abstract

Digital data is sampled for storage in a memory at a rate twice as fast as the memory is able to accept the samples.

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High Speed Digital Sampler

Digital data is sampled for storage in a memory at a rate twice as fast as the memory is able to accept the samples.

The memory normally stores 8-bit digital information representing time samples of a single-analog signal. The analog input samples are converted to digital signals by an analog-digital converter ADC, and are held in an input buffer for entry into the memory when the memory is ready to accept the digital data (at approximately 10 ns intervals). Data stored in the memory is accessed by an output buffer and transferred to an analog output through a digital-analog converter Digital data is received on eight input lines and sampled in two modes A and B, mode B sampling being twice as fast as mode A. In mode A, each input is amplified, compared to a predetermined level, delayed (to eliminate interline skew and asymmetry) and latched. The latches are sampled by a clock every 10 ns and their contents transferred to the input buffer. In mode B, only digital data from input lines 1, 3, 5, and 7 is processed. The sampling rate in each of these lines is doubled by storing, after a 5 ns delay, the initial state of a line in the latch associated with adjacent lines 2, 4, 6, and 8. The final state of a line appears in the latch associated with that line. Thus, each line is in effect sampled twice when the clock pulse transfers the contents of two latches for each line into the input buffer.

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