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Multiprocessing Storage Conflict Resolution Technique

IP.com Disclosure Number: IPCOM000078864D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Duke, KA: AUTHOR [+2]

Abstract

The drawing shows the storage control units of two processors which require data from a common memory system, which can process many requests simultaneously. All three are synchronized with a common clock cycle. The memory can accept one data request from one processor in each cycle. If it receives two requests in the same cycle it rejects one by some arbitrary decision process.

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Multiprocessing Storage Conflict Resolution Technique

The drawing shows the storage control units of two processors which require data from a common memory system, which can process many requests simultaneously. All three are synchronized with a common clock cycle. The memory can accept one data request from one processor in each cycle. If it receives two requests in the same cycle it rejects one by some arbitrary decision process.

Only one processor may access any particular item of data at any time. Each processor must therefore interrogate the other when requesting data from memory. Interrogation takes a finite time and to improve performance. it is executed in parallel with the data request to memory. A conflict arises when both processors request the same data item. Each processor transmits a copy of the data identifier (e.g. address) both to the memory system and to the other processor. If it receives the same identifier from the other processor within a time interval which is measurably less than the transmission time between the processors, it assumes that the other processor transmitted first and cancels its own request. If the identifier arrives measurably later than the transmission time, the processor assumes that it transmitted first and lets its request to memory stand. If the identifier arrives essentially delayed by exactly the same transmission time, it Is assumed that both processors transmitted at the same time and each processor operates as if it transmitted first. The memory priority mechanism then rejects one request and thus determines which processor gets the data item.

When a processor requires a data item from the memory system, it places a data identifier (address) into a register (MA...