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Electrically Reprogrammable Floating Avalanche Injection MOS (FAMOS) Structure

IP.com Disclosure Number: IPCOM000078876D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

DiStefano, TH: AUTHOR [+2]

Abstract

Recently, a memory element was developed the Floating-Gate Avalanche-Injection metal-oxide semiconductor (MOS) or (FAMOS) device Information in the form of charge is stored on an electrically isolated or floating gate of an MOS transistor. Surface avalanche at one of the transistor junctions is used to inject electrons through an insulating coating and onto the gate. In the FAMOS device 1 represented in Fig. 1, electrons are injected into the SiO(2) insulator 2 by avalanche breakdown of the source (p+) 3 to substrate (n) 4 junction. Erasure or dissipation of the gate charge is quite difficult to achieve in the present FAMOS device, because no electrical connections are made to the floating gate 5.

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Electrically Reprogrammable Floating Avalanche Injection MOS (FAMOS) Structure

Recently, a memory element was developed the Floating-Gate Avalanche- Injection metal-oxide semiconductor (MOS) or (FAMOS) device Information in the form of charge is stored on an electrically isolated or floating gate of an MOS transistor. Surface avalanche at one of the transistor junctions is used to inject electrons through an insulating coating and onto the gate. In the FAMOS device 1 represented in Fig. 1, electrons are injected into the SiO(2) insulator 2 by avalanche breakdown of the source (p+) 3 to substrate (n) 4 junction. Erasure or dissipation of the gate charge is quite difficult to achieve in the present FAMOS device, because no electrical connections are made to the floating gate 5. The method which is used to destroy charge on the floating gate involves exposure of the device to ionizing radiation, such as UV light or X-rays. Since irradiation is not a positive and well understood method and can damage the device, this technique of erasure is unacceptable.

A method of erasing charge on floating gate 5 and several structural embodiments in practical devices are described below. A general form of the new device, shown in Fig. 2, combines the FAMOS device 1 with a "clearing electrode" 6, which is separated from floating gate 5 by a nonlinear insulator 7. An insignificantly small amount of current flows between gate 5 and clearing electrode 6, at the small voltages normally found in the operating device. However, an appreciable amount of current flow can be induced between them by a relatively high voltage on clearing electrode 6. At such high fields, a nonlinear conductance between gate 5 and clearing electrode 6 will rise by several orders of magnitude, in order to pass the gate discharge current. Of course, this electric field should not be so high that a dielectric breakdown is produced. The conductance between gate 5 and clearing electrode 6 must increase nonlinearly to an appreciable value, at an average field which is much lower than the dielectric breakdown strength. Several suitable systems exhibiting nonlinear conduction are suggested later. Then, by using an appropriate, reasonably small bias on clearing electrode 6, gate 5 of FAMOS device 1 can be made to store charge or to drain any charge it may hold.

A normal cycle of operation for the device is outlined in Figs. 3A-3C, which shows an electronic energy diagram for the device. The various device elements of Fig. 2 are identified by the same reference numbers in Figs. 3A-3C. The initial configuration shown in Fig. 3A is chosen, such that a small electric field at the semiconductor surface induces majority charge carriers in semiconductor 4. No surface channel is formed in the MOS transistor, and the device is in the off state. Negative charge can be injected onto gate 5 by an avalanche breakdown of the source 3-substr...