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Charge Controlled 6-Device Memory Cell

IP.com Disclosure Number: IPCOM000078878D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Straehle, W: AUTHOR [+2]

Abstract

Field-effect transistors (FET's) 1 to 6 form a known 6-device FET memory cell, which can be accessed via bit lines B0, B1 and word line WL. The stored information is represented by the respective charge state of the node capacities of nodes N1, N2. In order to ensure that such a memory cell or an array of such memory cells has a low-total power dissipation, nodes N1, N2 are not continuously recharged via load devices 3, 4 but at particular time intervals. To this end, point P is subjected to a positive potential until the off-node has been charged to abt. Vt + 1V (Vt being the threshold voltage). The leakage current flowing out of off-node N1 or N2 during the power-down periods discharges this node, until a critical threshold for the cell stability has been reached.

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Charge Controlled 6-Device Memory Cell

Field-effect transistors (FET's) 1 to 6 form a known 6-device FET memory cell, which can be accessed via bit lines B0, B1 and word line WL. The stored information is represented by the respective charge state of the node capacities of nodes N1, N2. In order to ensure that such a memory cell or an array of such memory cells has a low-total power dissipation, nodes N1, N2 are not continuously recharged via load devices 3, 4 but at particular time intervals. To this end, point P is subjected to a positive potential until the off-node has been charged to abt. Vt + 1V (Vt being the threshold voltage). The leakage current flowing out of off-node N1 or N2 during the power-down periods discharges this node, until a critical threshold for the cell stability has been reached.

By the propcsed arrangement, the lower threshold of a cell node is sensed on an equivalent memory cell with the aid of a sensing circuit 7, amplified and applied to a recharge control switch 8 switching P to a positive potential. Via sensing circuit 9 the upper threshold is sensed and recharging is terminated.

The arrangement described thus permits memory contents being recharged at time intervals determined by the charge state of the equivalent memory cell, rather than at fixed intervals. Due to the good tracking of individual memory cells of integrated semiconductor memories, it is sufficient to match the threshold of an equivalent cell, so that the output sign...