Browse Prior Art Database

Vertically Integrated Logic Technology

IP.com Disclosure Number: IPCOM000078919D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Gillett, JB: AUTHOR

Abstract

Vertically integrating logic circuits increases packing density in a semiconductor wafer. Also, surface wiring for logical interconnections is increased because wiring for power distribution is eliminated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Vertically Integrated Logic Technology

Vertically integrating logic circuits increases packing density in a semiconductor wafer. Also, surface wiring for logical interconnections is increased because wiring for power distribution is eliminated.

In Fig. 1, P+ semiconductor wafer 10 is processed to have diffused regions 12' and 12'' of N+ conductivity. An epitaxial layer 14 of N- characteristic is formed on the surface of the wafer 10. A P diffusion 16 is formed in the epitaxial layer. Simultaneously the N+ regions 12' and 12'' out-diffuse into the epitaxial layer 14. A diffusion 18 of N+ conductivity type is formed in the diffusion 16. Contacts 20, 22 and 24 are suitably formed on the surfaces of the wafer 10 as output, input and supply terminals, respectively, of the circuit shown in Fig. 2. The N+ regions 12' and 12'' form the emitter of Q2, whose base is the P diffusion 16 and whose collector is the N+ diffusion 18. The PNP Q1 is formed by emitter P+ 10, base N- 14 and collector P 16. The relatively low injection from the wafer into the N+ regions 12' and 12'' has negligible effect on the useful h(FE) of Q1.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]