Browse Prior Art Database

Sense Latch for One Device Memory Cell

IP.com Disclosure Number: IPCOM000078938D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

This is a high-density, low-power, high-performance complementary metal-oxide semiconductor (CMOS) regeneration circuit for use with a dynamic, single-device memory cell. Fig. 1 illustrates the memory cell comprising transistor TM and capacitor C(m), and the CMOS sense latch circuit comprising transistors T1 through T8.

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Sense Latch for One Device Memory Cell

This is a high-density, low-power, high-performance complementary metal- oxide semiconductor (CMOS) regeneration circuit for use with a dynamic, single- device memory cell. Fig. 1 illustrates the memory cell comprising transistor TM and capacitor C(m), and the CMOS sense latch circuit comprising transistors T1 through T8.

Referring to Figs. 1 and 2, at the beginning of the memory cycle-the left bit (L.B.) line and the right bit (R.B.) line are charged to level V(L) through devices T1, T2, T3 and T4, when voltage pulses are impressed on terminals R and R. The voltage V(L) can be given by the formula:
V(L) = V(H) over 2 - V(T). where V(T) is the threshold voltage of TM.

When the word line (W. L.) is brought to a level of V(H), this results in a charge transfer which generates a signal voltage delta V on L. B. and R. B.

At this point pulses are applied, as indicated in Fig. 2, to terminals CS and CS. If the potential at node 3 is initially O V, the potential at line L. B. is delta V lower than the line R. B. Then after pulses CS and CS are applied, line L. B. is discharged to ground via device T6 and line R. B. is charged up to V(H) via device T7; and O V is restored in cell C(M) through TM.

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