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Patch Mechanism for a Read Only Control Storage

IP.com Disclosure Number: IPCOM000078963D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Dunbar, RG: AUTHOR [+4]

Abstract

Sometimes, after a data-processing machine is released, it is desirable to improve its performance significantly. A common method of doing this is to add an "accelerator package" (e.g., ROS 4, high-speed data flow 5) to the existing machine (e.g., control store 10, data flow 9), to reduce the execution times of the high-usage operations and let the low-usage operations (i.e. Input/Output and rarely used functions) remain the same. It is also important that the accelerator package remains relatively inexpensive for the increased performance obtained. One of the most significant components as far as price/performance is concerned, is the control storage. Read/write control storage is flexible in that it is easy to change, but it tends to be slower and more expensive than a read-only storage (ROS).

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Patch Mechanism for a Read Only Control Storage

Sometimes, after a data-processing machine is released, it is desirable to improve its performance significantly. A common method of doing this is to add an "accelerator package" (e.g., ROS 4, high-speed data flow 5) to the existing machine (e.g., control store 10, data flow 9), to reduce the execution times of the high-usage operations and let the low-usage operations (i.e. Input/Output and rarely used functions) remain the same. It is also important that the accelerator package remains relatively inexpensive for the increased performance obtained. One of the most significant components as far as price/performance is concerned, is the control storage. Read/write control storage is flexible in that it is easy to change, but it tends to be slower and more expensive than a read-only storage (ROS). A primary drawback to a ROS for control storage, has always been the long period of time between the discovery of a coding error and its correction. The drawing illustrates an improved method of temporarily patching a ROS (which is as fast as a read/write control store) until permanent correction can be made.

There is a patch stack 1 which contains one-bit storage for every OP (operation) code. During I (instruction) cycles, the stack is read out and the bit corresponding to the OP code being executed is checked via latch 2 and AND circuit 3. If the bit is on (logical 1) and the OP code being executed is one originally intended to be executed from the ROS 4 via the high-speed data flow 5, a patch address will be forced into the ROS address register 6 at the end of 1 cycles. This will, in turn, read out a control...