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Wraparound Elimination in Closely Packed Video Shift Registers

IP.com Disclosure Number: IPCOM000078973D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Casler, DH: AUTHOR

Abstract

Between video scans in an optical character recognition (OCR) machine, time is often required to perform operations based on logical measurements of the video passing into and out of the video shift register during the previous scan. This time, denoted as retrace time, has normally been generated by adding additional shift register length to each scan, thus delaying the transfer of video information from one scan of the register to the next by the desired retrace time. This technique eliminates the need for additional register length by stopping the shift register at the end of each scan. A counter generates retrace time and at the end of retrace, the shift register is started to advance video one scan.

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Wraparound Elimination in Closely Packed Video Shift Registers

Between video scans in an optical character recognition (OCR) machine, time is often required to perform operations based on logical measurements of the video passing into and out of the video shift register during the previous scan. This time, denoted as retrace time, has normally been generated by adding additional shift register length to each scan, thus delaying the transfer of video information from one scan of the register to the next by the desired retrace time. This technique eliminates the need for additional register length by stopping the shift register at the end of each scan. A counter generates retrace time and at the end of retrace, the shift register is started to advance video one scan.

Video bits are advanced into the serial input of video register 10 during the first N counts of the video shift register (VSR) counter 11, where N is the number of bits in each video scan. Each scan of the video register is also N-bits long. At N time, the register advance gate latch 12 is reset, which stops the advance pulses to the video and gating registers. During the next M counts of VSR counter 11, video register 10 is not shifted. These M counts are the retrace portion of a VSR cycle. The cycle is then repeated for the next data scan.

At the end of each VSR cycle, the bottom of the video scan is located in the bottom row of video register 10. Similarly, the top of the video scan is in the top row. During the shifting phase of the VSR cycle, the bottom bit of the video scan will be adjace...