Browse Prior Art Database

Video Buffer for Preprocessing in Character Recognition Systems

IP.com Disclosure Number: IPCOM000078974D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Kimmel, MJ: AUTHOR

Abstract

Many optical character recognition (OCR) systems require two separate passes through lines of video information: a prescan for preprocessing functions such as size normalization, position registration, data consolidation, etc., and a read scan for recognition of the preprocessed video data. For a scanner 1 having mechanical motion or other timing constraints, it is undesirable to optically read each video line twice. If a programmable processor 2 is used for the recognition function, it is desirable to use this processor for the preprocessing functions also, instead of adding pipelined logic in the video path between scanner 1 and processor 2. Both requirements may be met by the proper storage and retrieval of an electronic image of the video data.

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Video Buffer for Preprocessing in Character Recognition Systems

Many optical character recognition (OCR) systems require two separate passes through lines of video information: a prescan for preprocessing functions such as size normalization, position registration, data consolidation, etc., and a read scan for recognition of the preprocessed video data. For a scanner 1 having mechanical motion or other timing constraints, it is undesirable to optically read each video line twice. If a programmable processor 2 is used for the recognition function, it is desirable to use this processor for the preprocessing functions also, instead of adding pipelined logic in the video path between scanner 1 and processor 2. Both requirements may be met by the proper storage and retrieval of an electronic image of the video data.

Video buffer 10 stores video data from scanner 1 in a queue and outputs it on demand to processor 10, in the same order as it was received. At the beginning of a video field, an instruction in processor 2 places control bits in an external register which reset the contents of TOP1 register 11, TOP2 register 12 and BOT register 13 through gates 14-16 connected to control lines 17. These registers specify the locations in video storage module 18 of the entry end (bottom) and exit end (top) of the video queue. The use of two top registers allows processor 2 to access the contents of storage module 18 twice for different purposes.

After registers 11-13 have been reset, digitized video in video input register 19 is asynchronously entered through gate 20 into a storage location, by gating the co...