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Flip Flop True Complement Generator

IP.com Disclosure Number: IPCOM000078986D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Cassidy, BM: AUTHOR [+2]

Abstract

This is a true-complement generator having a flip-flop coupled thereto to achieve gains, speed of information flow, and latch the state of the generator to hold the address once the input signal is removed. By balancing the load of the flip-flop to equal the load of the output transistor, power is reduced and the flip-flop and the output transistor of the generator will track each other, even when there are variations in temperature.

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Flip Flop True Complement Generator

This is a true-complement generator having a flip-flop coupled thereto to achieve gains, speed of information flow, and latch the state of the generator to hold the address once the input signal is removed. By balancing the load of the flip-flop to equal the load of the output transistor, power is reduced and the flip- flop and the output transistor of the generator will track each other, even when there are variations in temperature.

As shown in the figure, the base of a transistor T1 is coupled to receive an input address while the base of transistor T2 is held at a constant voltage. Transistor T11, coupled to the emitters of these transistors T1 and T2, serves as a current source and transistors T3 and T4, whose bases are coupled to the emitters of transistors T1 and T2, respectively, act as a current switch. At the beginning of a cycle, it will be assumed that node A is positive and an address signal is applied to the base of transistor T1. This causes transistor T1 to be turned on, such that the voltage at the base of transistor T6 reaches its turn-on voltage, and transistors T7 and T10 are turned on. When transistor T7 turns on the bases of transistors T8 and T9 are held low, causing transistors T10 to latch in the on condition. Thus, the output coupled to the emitter of transistor T10 is kept on, while the output at the emitter of transistor T9 is held off. Once the output transistor; i.e., in this case transistor T10, i...